(6) RAM & ROM techy stuff

AGC core memory & core ‘rope’ —

CORE MEMORY and CORE ROPE          —      [index]

Computer experience in 1969 with the HP2116 and its successors meant embracing core (RAM) memory as our technology reference. Yet we were unaware of the distinction between “cores” and “rope”, which as we now see is one of the most significant elements to building the AGC. CuriousMarc has excellent information in part 14 of his AGC series: [extract 70s to 300s]

Frank O’Brien’s book has more details.  On page 36 he states:

“Core rope, as contrasted with conventional read/write core memory, does not depend on the magnetization of the cores. Rather, the ferrite rings act as transformers, and the contents of a word are dependent on the wiring scheme of the memory and not on any particular magnetic state .  . . .  it is important to remember that these cores are simply torodial shaped transformers, and are not themselves magnetized.

This last sentence, although technically correct, was initially confusing, as clearly the cores are required and if they are not themselves magnetized, then what purpose do they fulfill?  Is the answer that they are magnetized, but only during the memory operation of fetching from the ROM – just the “1”s, and only at that moment? Well, as a transformer action, a pulse generator, but this imagery was less helpful.

Some alternative wording is here on page 93 of the MIT report of 1972 – describing the core rope – which says: “After the selected core has switched and the inhibit currents are removed, a reset current is passed through all cores, Only the core that was just set will change state, and the sense amplifiers may be gated on during either the set or the reset part of the cycle to read information out of the memory.”


If we still have difficulty imagining the essence of these two “core” juxtapositions, try this:  1) Core RAM memory can retain its content (AGC RAM memories have been analyzed decades later to find out what the computer was doing and the status of many variables). 2) In a different way, the core rope ‘ROM’ willingly gives up its secrets — because, unless the wires or components in the core rope have been damaged, the rope code can still be “read” because, even though nothing is stored in the cores, information can be regenerated from each address just as it was during operation. ‘Content’ is determined by the threading pattern of the wires, using the cores to detect the ‘content’ of each address — valid only during that memory operation cycle.


CoreRope_hrst.mit.edu_hrs_apollo_public_images_Plate_19_smallEach of these cores is actually much larger than those in the core RAM – each core is used multiple (192) times in the AGC requiring there be multiple sets of wires threaded through or around them (see footnote) – which brings the total wires to the physical space limit of the core. The manufacturing process of the core ropes can be seen in the video above and those linked here and here. Total bits per module is 512 physical cores x 192 sense lines — so x 6 modules gives 589,824 bits = 36,864 words (15 bits + parity).

Photo of the core rope © Raytheon. Diagram from MIT,redrawn in Ken Shirriff’s blog.

CuriousMarc and the team have been able to read a real core rope from an AGC located at the Mountain View (CA) computer museum. The work performed here along with superb video documenting is amazing and such an important addition to our collective history.


The address selection and readout of the rope is extremely complicated, with contradictory explanations on the web not helping. We know that it is the threading of the cores, or bypassing of the cores which determines ‘content’. We know that there are physically six rope modules and each module consists of two layers of 256 physical cores – so there are in total 6 x 256 x 2 physical cores = 3,072 physical cores. In a traditional 16-bit core memory this gives us a total storage of 192 words – so hopelessly short of what we need in the rope ROM.

In fact 192 times too little ! Which means, without understanding the complex addressing scheme (*), we can already know that each physical core must somehow represent 192 conventional cores or memory locations (192 x 192 = 36,864). To put this into words (16-bit words – the AGC memory is 15 bits plus parity, so always 16 bits), each physical core must somehow represent 12 words of the total ROM.

(*) To read a well-written description of the addressing scheme, refer to the notes section of Ken Shirriff’s blog.